Advance Computer Architecture (CS501)

1. ________ is the time for first bit of the message to arrive at the receiver including delays.

   1. Transmission Time
   2. Latency
   3. Transport Latency
   4. Time of Flight

2. In floating point representations ______ is also called mantissa.

   1. Sign
   2. Base
   3. Significant
   4. Exponent

3. Which one of the following is a term used to describe a storage systems' resilience to disk failure through the use of multiple disks and by the use of data distribution and correction techniques?

   1. Interrupt handling
   2. Programmed I/O
   3. Polling
   4. RAID

4. For ________ of an error we just need to know that there exists an error.

   1. Correction
   2. Detection
   3. Both Correction and Detection
   4. None of the given

5. Raid Level ________ is not a true member of the RAID family.

   1. 0
   2. 2
   3. 3
   4. 4

6. Taking control of the system bus for a few bus cycles is known as ________.

   1. Bus Stealing
   2. Cycle Stealing
   3. Cycle Transfering
   4. None of the given

7. By which file extension does the FALCON-A Assembler loads a FALCON-A assembly file?

   1. .asmfa
   2. .org
   3. .exe
   4. .src

8. The ________ can also be used anywhere in the source file to force code at a particular address in the memory.

   1. .end directive
   2. .start directive
   3. .label directive
   4. .org directive

9. Falcon-A Simulator loads a FALCON-A binary file with a ________ extension and presents its contents into different areas of the simulator.

   1. .bin
   2. .binfa
   3. .fa
   4. None of the given

10. In computers, floating-point representation uses ________ to encode significant, exponent and their sign in a single word

    1. Decimal Numbers
    2. Binary Numbers
    3. Octal Numbers
    4. Hexa decimal Numbers

11. A 64k x 1 Static RAM Chip has a cell array which consists of ________ row(s) and ________ column(s).

    1. 64, 1
    2. 1, 64
    3. 64, 256
    4. 256, 256

12. ________ is non volatile i.e it retains the information in it when power is removed from it.

    1. RAM
    2. Hard Disc
    3. ROM
    4. Cache

13. Multiple copies of the same data can exist in memory hierarchy simultaneously. The Cache needs updating mechanism to prevent old data vlues from being used. This is the problem of ________.

    1. Cache Miss
    2. Dirty bit
    3. Cache Coherence
    4. White Allocate

14. Which one the following interrupts is initiated with an INT instruction?

    1. Hardware
    2. Software
    3. Both hardware and Software
    4. None of the given

15. In which one of the following methods, does the CPU poll to identify the interrupting module and branches to an interrupt service routine on detecting an interrupt?

    1. Daisy Chain
    2. Software Poll
    3. Multiple interrupt lines
    4. All of the given

16. Where does the processor store the address of the first instruction of the ISR?

    1. Interrupt vector
    2. Interrupt request
    3. Interrupt handler
    4. All of the given

17. A software routine performed when an interrupt is received by the computer is called as __________.

    1. Interrupt
    2. Interrupt handler
    3. Exception
    4. Trap

18. Which is the last instruction of the ISR that is to be executed when the ISR terminates?

    1. IRET
    2. IRQ
    3. INT
    4. NMI

19. In which one of the following methods for resolving the priority, the device with the highest priority is placed in the first position, followed by lower-priority devices up to the device with the lowest priority, which is placed last in the series?

    1. Asynchronous
    2. Daisy-Chaining Priority
    3. Parallel
    4. Semi-synchronous

20. Every time you press a key, an interrupt is generated.
    This is an example of

    1. Hardware interrupt
    2. Software interrupt
    3. All of the given
    4. None of the given

21. All ________ interrupts have priority over all ________ interrupts

    1. internal, external
    2. external, internal

22. Keyboard Interrupt (INT 9) is an example of ________ interrupt.

    1. Hardware
    2. Software

23. Which one of the following is NOT a technique used when the CPU wants to exchange data with a peripheral device?

    1. Direct Memory Access (DMA)
    2. Interrupt driven I/O
    3. Programmed I/O
    4. Virtual Memory

24. ________ the device usually means reading its status register every so often until the device's status changes to indicate that it has completed the request.

    1. Interrupting
    2. Masking
    3. Polling
    4. Executing

25. ________ is a technique in which some of the CPU’s address lines forming an input to the address decoder are ignored.

    1. Microprogramming
    2. Instruction pre-fetching
    3. Pipelining
    4. Partial decoding

26. Connection to a CPU that provides a data path between the CPU and external devices, such as a keyboard, display, or reader is called ___________.

    1. Buffer
    2. I/O port
    3. Memory mapping
    4. Processor

27. ________ is an electrical pathway through which the processor communicates with the internal and external devices attached to the computer.

    1. Computer Bus
    2. Hazard
    3. Memory
    4. Disk

28. Identify the type of serial communication error condition in which a 0 is received instead of a stop bit (which is always a 1)?

    1. Framing error
    2. Parity error
    3. Overrun error
    4. Under-run error

29. In the little-endian format exchanging data between computers, the data transmitted by one will be received in a "swapped" form by the other.

    1. Organized
    2. Signals
    3. Swapped
    4. Arranged

30. The information about interrupt vector is given in 8-bits, from bit 0 to 7, which is translated to bit ________ on the data bus.

    1. 16 to 23
    2. 11 to 18
    3. 0 to 7
    4. 8 to 15

31. ________ is the simplest form for representing a signed number.

    1. Biased Representation
    2. Diminished Radix Compliment Form
    3. Sign Magnitude Form
    4. None of the given

32. ________ signal is used in printer with DB-25 interface to reset its controller.

    1. #PE
    2. #STROB
    3. #INT
    4. #SLCT

33. A component connected to the system bus and having control of it during a particular bus cycle is called ________.

    1. Slave component
    2. Master component
    3. System bus
    4. Buffer component

34. Most parallel I/O ports used with peripheral devices are mapped on a range of ________.

    1. Bus addresses
    2. Direct memory Access
    3. contiguous addresses
    4. Cache

35. ________ is/are example(s) of synchronous communication.

    1. Register to Register
    2. Register to Memory
    3. Memory to Memory
    4. All of the given

36. In a printer with DB-25 interface, ________ signal is better for edge triggered systems.

    1. BUSY#
    2. PE#
    3. ACKNLG#
    4. STROB#

37. For input ports, the incoming data should be placed on the data bus only during the I/O read bus cycle. For this purpose, ________ are used.

    1. Flip Flops
    2. Tri-state Buffers
    3. AND Gates
    4. Registers

38. How can you define an interrupt?

    1. A process where an external device can speed up the working of the microprocessor
    2. A process where memory can speed up programs execution speed
    3. A process where an external device can get the attention of the microprocessor
    4. A process where input devices can takeover the working of the microprocessor

39. ET = ________.

    1. CP x IC x T
    2. CPI x IC x T
    3. CPI / IC x T
    4. None of the given

40. In 8086/8088 processor, interrupt vector table is located at the memory location ________.

    1. 0
    2. 4
    3. 256
    4. 1024

41. Why DMA is faster than Programmer I/O technique because?

    1. DMA transfers data directly using CPU
    2. DMA transfers data directly without using CPU
    3. DMA uses buffers with CPU
    4. DMA uses interrupted driven I/O

42. Given an m-digit base b number x, the ________ of x is $$x^c = (b^m - x) \; mod \; b^m$$

    1. Radix Compliment
    2. Diminished Radix Compliment
    3. Signed Magnitude Form
    4. Biased Representation

43. How does DMA saves CPU time?

    1. By controlling data transfer between I/O device and memory directly.
    2. By storing all data in a buffer to be later transferred to the CPU.
    3. By periodically polling.
    4. By issuing an interrupt request to the CPU to request attention.

44. Select the parts of a hard disk?

    1. Header only
    2. Data section and a trailer
    3. Data section only
    4. Header, data section and a trailer.

45. ________ allows a peripheral to read and write memory without intervention by the CPU.

    1. Programmed I/O
    2. Interrupt driven I/O
    3. Direct memory access (DMA)
    4. Polling

46. The Pentium does allow the use of some port of its ________ accumulator register EAX

    1. 8 bits
    2. 16 bits
    3. 32 bits
    4. 64 bits

47. Which I/O technique will be used by a sound card that may need to access data stored in the computer's RAM?

    1. Programmed I/O
    2. Interrupt driven I/O
    3. Direct memory access (DMA)
    4. Polling

48. A computer interface is an ________ circuit that matches the requirements of the two subsystems between which it is connected

    1. Digital
    2. Electronic
    3. Primary
    4. Obituary

49. Every interrupt handler has an interrupt return (IRET) instruction, this instruction is an example of ________ return.

    1. NEAR
    2. FAR
    3. SHORT
    4. RELATIVE

50. Identify the following type of serial communication error condition:
    "The prior character that was received was not still read by the CPU and is over written by a new received character."

    1. Framing error
    2. Parity error
    3. Overrun error
    4. Under-run error

51. What is the status of the ACKNLG# signal when a character is completely received by the printer?

    1. It goes from low to high
    2. It goes from high to low
    3. It toggles its state
    4. It remains unaffected

52. How Interrupt driven I/O is better than polling because?

    1. Interrupt driver I/O is easy to design.
    2. Interrupt driver I/O is enhanced version of polling.
    3. Interrupt driver I/O does not waste time on checking which device is available.
    4. Interrupt driver I/O is easy to program.

53. Along with information bits we add up another bit which is called the ________ bit.

    1. CRC
    2. Hamming
    3. Error Detection
    4. Parity

54. Tri-state buffers are used for removing ________.

    1. Instruction collision
    2. bus collision
    3. Instruction contention
    4. bus contention

55. In which technique does the hardware directly access host memory for reading or writing independent of CPU?

    1. Direct Memory Access (DMA)
    2. Programmed I/O
    3. Interrupt driven I/O
    4. Polling

56. The main issue/s in error control is/are ________.

    1. Detection of Error
    2. Correction of Error
    3. Both Detection of Error and Correction of Error
    4. Avoidance of Error

57. The source file of FALSIM should contain ________ text only.

    1. Unicode
    2. ASCII
    3. ANSI
    4. UTF

58. The directive ________ is used to define variables.

    1. .equ
    2. .db
    3. .sw
    4. .org

59. human works with base 10 and computers work with base ________.

    1. 8
    2. 10
    3. 2
    4. 16

60. The ________ can be determined from the number of platters and the number of tracks.

    1. Speed of processing
    2. execution time
    3. storage capacity
    4. Latency

61. The conversion of numbers from a representation in one base to another is known as ________.

    1. Radix Conversion
    2. Number Representation
    3. Decimal representation
    4. Hexadecimal Representation

62. ________ is/a re defined as the number of instructions processed per second.

    1. Throughput
    2. Latency Time to process 1 request.
    3. Throughput and Latency
    4. None of the given

63. A user program has to delete a file. The user program will be executing in the user mode. When it makes the specific system call to delete the file, an interrupt will be generated, this will cause the processor to halt its current activity and switch to supervisor mode. Once in supervisor mode, the operating system will delete the file and then control will return to the user program. This is an example of

    1. Hardware interrupt
    2. Software interrupt
    3. Exception
    4. All of the given

64. When is the “Divide error interrupt" generated?

    1. When an attempt is made to divide by decimal number
    2. When an attempt is made to multiply by zero
    3. When an attempt is made to divide by zero
    4. When negative number is stored in a register

65. What should be the behavior of interrupts during critical sections?

    1. Must remain disable
    2. Must remain Enable
    3. Can be either enable or disable
    4. only important interrupts be enable

66. ________ operation is required to change the processor’s state to a known, defined value.

    1. Change
    2. Reset
    3. Update
    4. None of the given

67. For any of the instructions that are a part of the instruction set of the SRC, there are certain _________required which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.

    1. Register
    2. Control signals
    3. Memory
    4. None of the given

68. ________ control signal enable the input to the PC for receiving a value that is currently on the internal processor bus.

    1. LPC
    2. INC4
    3. LC
    4. I

69. FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC ________ wide.

    1. 8-bits
    2. 16-bits
    3. 32-bits
    4. 64-bits

70. Which one of the following registers holds the address of the next instruction to be executed?

    1. Accumulator
    2. Address Mask
    3. Instruction Register
    4. Program Counter

71. Which type of instructions help in changing the flow of the program as and when required?

    1. Arithmetic
    2. Control
    3. Data transfer
    4. Floating point

72. What is the instruction length of the FALCON-A processor?

    1. 8-bits
    2. 16-bits
    3. 32-bits
    4. 64-bits

73. What is the instruction length of the FALCON-E processor?

    1. 8 bits
    2. 16 bits
    3. 32 bits
    4. 64 bits

74. What is the instruction length of the SRC and Falcon E processor?

    1. 8 bits
    2. 16 bits
    3. 32 bits
    4. 64 bits

75. Which one of the following is the memory organization of EAGLE processor?

    1. 8-bits
    2. 16-bits
    3. 32-bits
    4. 64-bits

76. Which type of instructions enables mathematical computations?

    1. Arithmetic
    2. Control
    3. Data transfer
    4. None of the given

77. Which one of the following portions of an instruction represents the operation to be performed?

    1. Address
    2. Instruction code
    3. Opcode
    4. Operand

78. Which type of instructions load data from memory into registers, or store data from registers into memory and transfer data between different kinds of special-purpose registers?

    1. Arithmetic
    2. Control
    3. Data transfer
    4. Floating point

79. Which one of the following is a binary cell capable of storing one bit of information?

    1. Decoder
    2. Flip-flop
    3. Multiplexer
    4. Diplexer

80. Which one of the following is a bi-stable device, capable of storing one bit of information?

    1. Decoder
    2. Flip-Flop
    3. Multiplexer
    4. Diplexer

81. Which one of the following languages presents a simple, human-oriented language to specify the operations, register communication and timing of the steps that take place within a CPU to carry out higher level (user programmable) instructions?

    1. Assembly Language
    2. OOP(Object Oriented Language)
    3. RTL (Register Transfer Language)
    4. UML(Unified Modeling language)

82. What does the RTL expression [M(1234)] means?

    1. The contents of memory whose address is 1234.
    2. The contents of data register 1234
    3. The effective address of register 1234
    4. The address of memory whose address is 1234.

83. Which instruction is used to store register to memory using relative address?

    1. ld instruction
    2. ldr instruction
    3. lar instruction
    4. str instruction

84. The instruction ________ will load the register R3 with the contenets of the m\emory location M [PC+56]

    1. Add R3, 56
    2. lar R3, 56
    3. ldr R3, 56
    4. str R3, 56

85. Type A of SRC has which of the following instructions?
    

    1. andi, instruction
    2. No operation or nop instruction
    3. lar instruction
    4. ldr instruction
    5. Stop operation or stop instruction

    1. 1 & 2
    2. 2 & 3
    3. 3 & 5
    4. 2 & 5

86. An instruction that specifies one operand in memory and one operand in a register would be known as a ________ address instruction.

    1. 2-1/2
    2. 1-1/2
    3. 0
    4. 2

87. Which one of the following instructions is used to load register from memory using a relative address?

    1. la
    2. lar
    3. ldr
    4. str

88. Which one of the following is an address (binary bit pattern) issued by CPU?

    1. Memory
    2. Effective
    3. Base
    4. Nex t instruction

89. In ________ address mode, the actual data is stored in the instruction.

    1. Direct
    2. Indirect
    3. Immediate
    4. Relative

90. In which one of the following addressing modes, the operand does not specify an address but it is the actual data to be used.

    1. Direct
    2. Indirect
    3. Immediate
    4. Relative

91. 
    In this figure, the constant value specified by the immediate field is added to the register value, and the resultant is the index of memory location that is referred i.e. Effective Address = A + (content of R) . Identify the addressing mode.

    1. Displacement
    2. Immediate
    3. Indexed
    4. Relative

92. Which one of the following registers store a previously calculated value or a value loaded from the main memory?

    1. Accumulator
    2. Address Mask
    3. Instruction Register
    4. Program Counter

93. Which field of the machine language instruction is the “type of operation” that is to be performed?

    1. Op-code
    2. CPU registers
    3. Memory cells
    4. I/O locations

94. An ________ is a program that takes basic computer instructions and converts them into a pattern of bits that the computer's processor can use to perform its basic operations.

    1. Assembler
    2. Debugger
    3. Editor
    4. Console

95. In machines where instructions can be executed in parallel or out of order, two additional hazards can occur: WAW and ________.

    1. WAR
    2. RAW
    3. RAR
    4. None of the given

96. The external interface of FALCON-A consists of a ________ address bus and ________ a data bus.

    1. 8-bit. 8-bit
    2. 16-bit. 16-bit
    3. 16-bit. 24-bit
    4. 16-bit. 32-bit

Select a course code for Objective Questions:

ACC311 ACC501 BIF101 BIF401 BIF501 BIO101 BIO201 BIO202 BIO203 BIO204 BIO301 BIO302 BIO303 BIO401 BIO503 BNK603 BT101 BT201 BT301 BT302 BT401 BT402 BT403 BT404 BT405 BT406 BT501 BT504 BT505 BT604 CHE201 CHE301 CS001 CS101 CS201 CS202 CS204 CS301 CS302 CS304 CS311 CS401 CS402 CS403 CS408 CS501 CS502 CS504 CS506 CS508 CS601 CS602 CS604 CS605 CS607 CS609 CS610 CS614 CS707 CS710 ECO401 ECO402 ECO403 ECO404 EDU302 EDU401 EDU402 EDU501 EDU601 ENG101 ENG201 ENG301 ENG501 FIN611 FIN624 FIN625 ISL201 IT430 MCM101 MCM301 MGMT623 MGT101 MGT211 MGT301 MGT401 MGT402 MGT501 MGT502 MGT503 MGT510 MGT601 MGT603 MKT501 MKT610 MKT630 MTH101 MTH202 MTH302 MTH501 MTH601 MTH634 PAK301 PHY101 PHY301 PSY101 PSY403 PSY502 PSY512 SOC101 SOC301 SOC401 STA301 STA630 STA641 ZOO102 ZOO401 ZOO501 ZOO502 ZOO503 ZOO504 ZOO505 ZOO506 ZOO510 ZOO630

Select a course code for Subjective Questions:

ACC311 CS001 CS101 CS201 CS301 CS607 CS701 CS702 CS703 CS704 CS707 CS708 CS710 CS711 CS718 CS721 CS724 ECO401 ECO403 ENG101 ENG301 MGT703 MTH501 STA301