Multiple Choice Questions (MCQs)
In DRAM read cycle R /W- signal is activated to read data which is made available on the ________ data line.
The Test Vector definition defines the test vectors for all the three counter inputs and ________ counter output/outputs.
When the transmission line is idle in an asynchronous transmission
Implementation of Latch is required almost ________ transistor.
In memory write cycle, the time for which the WE signal remains active is known as the ________.
The output of a NAND gate is ________ when all the inputs are one.
As data values are written or read from the RAM Stack Pointer Register increments or decrements its contents always pointing to the stack ________.
Subtractors also have output to check if 1 has been ________.
Consider the sum of weight method for converting decimal into binary value, ________ is the highest weight for 411.
The 64-cell array organized as 8 x 8 cell array is considered
A NOR based S-R latch is implemented using ________ gates instead of ________ gates.
In the keyboard encoder, how many times per second does the ring counter scan the key board?
The 74HC163 is a 4-bit Synchronous counter, it has ________ data output pins.
The ABEL Input file can use a ________ instead of the equation to specify the Boolean expressions.
Canonical form is a unique way of representing ________.
If the voltage drop across the active load is 0 volts due to absence of current the comparator output is a ________.
Two types of memories namely the first in-first out (FIFO) memory and last in first out (LIFO) are implemented using ________.
A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter.
The Adjacent 1s Detector accepts 4-bit inputs. If ________ adjacents 1s are detected in the input, the output is set to high.
A multiplexer with a register circuit converts
Which signal must remain valid in memory write cycle after data is applied at the data input lines and must remain valid for a minimum time duration tWD?
PALs tend to execute ________ logic.
Flash memory Operation are classified into ________ different operation.
Demorgan's two theorems prove the equivalency of the NAND and ________ gates and the NOR and ________ gates respectively.
GAL can be reprogrammed as instead of fuses E2CMOS logic is used which can be programmed to connect a ________ with a ________.
A SOP expression can be implemented by an ________ combination of gates.
The terminal count of a 4-bit binary counter in the UP mode is ________.
The ________ input overrides the ________ input.
For a down counter that counts from (111 to 000), if current state is "101" the next state will be ________.
The domain of the expression AB'CD + AB' + C'D + B is
Implementing the Adjacent 1s detector circuit directly from the function table based on the SOP form requires ________ gates for the 8 product terms (minterms) with an 8-input OR gate.
The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________ inputs.
For a Standard SOP expression, a ________ is placed in the cell corresponding to the product term (Minterm) present in the expression.
Why demultiplexer is called a data distributor?
In NAND based S-R latch, output of each ________ gate is connected to the input of the other ________ gate.
A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN mode is:
Which one flip-flop has an invalid output state?
If the number of samples that are collected is reduced by half, the reconstructed signal will be ________ from/to the original.
The maximum value, represented by a single hexadecimal digit is ________.
In distributed mode, for a 1024 x 1024 DRAM memory and a refresh cycle of 8 msec, each of the 1024 rows has to be refreshed in ________ when Distributed refresh is used.
The ________ gate and ________ gate implementation connected at the B input of the 4-bit Adder is used to allow Complemented or Un-Complemented B input to be connected to the Adder input.
If two numbers in BCD representation generate an invalid BCD number then the binary ________ is added to the result.
The ROM used by a computer is relatively ________ as it stores few byres of code used to Boot the Computer system on power up.
8-bit parallel data can be converted into serial data by using ________ multiplexer.
Two signals ________ and ________ provide the timing inputs to the State Machine.
The Static Ram (SRAM) is non-volatile and is not a ________ density memory as a latch is required to store a single bit of information.
In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated Circuit counters allow cascading of multiple counters together.
Implementation of the FIFO buffer in ________ is usually takes the form of a circular buffer.
Divide-by-32 counter can be achieved by using
An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________.
Consider A=1, B=0, C=1. A, B and C represent the input of three bit NAND gate, the output of the NAND gate will be ________.
Which of the following is a volatile memory?
You have to choose suitable option when your timer will reset by considering this given code: TRSTATE.CLK = clk; TMRST: = (TRSTATE = = NSY2) # (TRSTATE = = EWY2);
The Transition table is very similar to the ________ table.
The n flip-flops store ________ states.
The S-R latch has two inputs, therefore ________ different combinations of inputs can be applied to control the operation of the S-R latch.
UVERPROM is stands for
The next state table for REQ1, FLOOR1 and OPEN inputs indicates that the ________ can be pressed at any time either on the first floor or the second floor in elevator.
The FAST Model Page Access allows ________ memory read and access times when reading successive data values stored in consecutive locations on the same row.
Adding two octal numbers "36" and "71" result in ________.
Which of the following Output Equations determines the output of the State Machine?
The CONSTATE.CLK = Clock is used to indicate that the ________ state variables change on a clock transition.
Memory is arranged in ________.
The AND Gate performs a logical ________ function.
The NOR logic gate is the same as the operation of the ________ gate with an inverter connected to the output.
Cin is part of ________ Adder.
PLDs have In-System Programming (ISP) capability that allows the ________ to be programmed after they have been installed on a circuit board.
________ is used when the output is connected back to the input of the PAL or if the output pin is used as an input only.
________ Counters as the name indicates are not triggered simultaneously.
A 3-variable karnaugh map has
The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to read or write up to ________ location(s) using a single address.
The outputs of SR latches in elevator state machine are feed back to the ________ gate array for connection to the D-flipflops.
Select the mode of programming in which GAL16V8 can be programmed:
Select a course code for Objective Questions:
Select a course code for Subjective Questions: