Digital Logic Design (CS302)

1. Canonical form is a unique way of representing ________.

   1. SOP
   2. Minterm
   3. Boolean Expression
   4. POS

2. For a Standard SOP expression, a ________ is placed in the cell corresponding to the product term (Minterm) present in the expression.

   1. 0
   2. 1
   3. x (don't care condition)
   4. Any of given option depending on SOP term

3. Subtractors also have output to check if 1 has been ________.

   1. Primed
   2. Shifted
   3. Complemented
   4. Borrowed

4. A 3-variable karnaugh map has

   1. eight cells
   2. three cells
   3. sixteen cells
   4. four cells

5. Adding two octal numbers "36" and "71" result in ________.

   1. 213
   2. 123
   3. 127
   4. 345

6. Select the mode of programming in which GAL16V8 can be programmed:

   1. Simple Mode
   2. Complex Mode
   3. Registered Mode
   4. All of the given

7. If the number of samples that are collected is reduced by half, the reconstructed signal will be ________ from/to the original.

   1. Different
   2. Same
   3. Equal
   4. Opposite

8. GAL can be reprogrammed as instead of fuses E2CMOS logic is used which can be programmed to connect a ________ with a ________.

   1. column, row
   2. row, column
   3. column, column
   4. row, row

9. The AND Gate performs a logical ________ function.

   1. Addition
   2. Substraction
   3. Multiplication
   4. Division

10. Implementing the Adjacent 1s detector circuit directly from the function table based on the SOP form requires ________ gates for the 8 product terms (minterms) with an 8-input OR gate.

    1. 8 OR
    2. 8 AND
    3. 8 XOR
    4. 8 NOR

11. Consider the sum of weight method for converting decimal into binary value, ________ is the highest weight for 411.

    1. 64
    2. 128
    3. 256
    4. 512

12. A NOR based S-R latch is implemented using ________ gates instead of ________ gates.

    1. XOR, NAND
    2. NOR, XOR
    3. NOR, NAND
    4. OR, XOR

13. The NOR logic gate is the same as the operation of the ________ gate with an inverter connected to the output.

    1. AND
    2. NAND
    3. OR
    4. NOT

14. The ________ gate and ________ gate implementation connected at the B input of the 4-bit Adder is used to allow Complemented or Un-Complemented B input to be connected to the Adder input.

    1. AND, NOR
    2. AND, NOT
    3. AND, OR
    4. XOR, NAND

15. ________ is used when the output is connected back to the input of the PAL or if the output pin is used as an input only.

    1. Combinational Input/Output
    2. Combinational Output
    3. Combinational Input
    4. Programmable polarity

16. The Adjacent 1s Detector accepts 4-bit inputs. If ________ adjacents 1s are detected in the input, the output is set to high.

    1. 2
    2. 4
    3. 1
    4. 0

17. A SOP expression can be implemented by an ________ combination of gates.

    1. OR-XOR
    2. AND-NAND
    3. AND-OR
    4. XOR-NOR

18. Cin is part of ________ Adder.

    1. Half
    2. Full
    3. Single
    4. Double

19. The S-R latch has two inputs, therefore ________ different combinations of inputs can be applied to control the operation of the S-R latch.

    1. two
    2. four
    3. eight
    4. sixteen

20. Why demultiplexer is called a data distributor?

    1. The input will be distributed to one of the outputs
    2. The input will be selected for the output
    3. The output will be distributed to one of the inputs
    4. Single input to Single Output

21. 8-bit parallel data can be converted into serial data by using ________ multiplexer.

    1. 4-to-2
    2. 8-to-1
    3. 4-to-4
    4. 8-to-4

22. In NAND based S-R latch, output of each ________ gate is connected to the input of the other ________ gate.

    1. NOR, NAND
    2. NAND, NOR
    3. NOR, NOR
    4. NAND, NAND

23. The output of a NAND gate is ________ when all the inputs are one.

    1. Zero
    2. One
    3. Available
    4. Not available

24. PLDs have In-System Programming (ISP) capability that allows the ________ to be programmed after they have been installed on a circuit board.

    1. PLAs
    2. PALs
    3. PLDs
    4. EPROM

25. The maximum value, represented by a single hexadecimal digit is ________.

    1. "E"
    2. "F"
    3. "G"
    4. "H"

26. The domain of the expression AB'CD + AB' + C'D + B is

    1. A and D
    2. B only
    3. A, B, C and D
    4. None of the given

27. If two numbers in BCD representation generate an invalid BCD number then the binary ________ is added to the result.

    1. 1001
    2. 0110
    3. 1111
    4. 1100

28. Consider A=1, B=0, C=1. A, B and C represent the input of three bit NAND gate, the output of the NAND gate will be ________.

    1. Zero
    2. One
    3. Undefined
    4. No output as input is invalid

29. Demorgan's two theorems prove the equivalency of the NAND and ________ gates and the NOR and ________ gates respectively.

    1. Negative-OR, Negative-AND
    2. Negative-AND, Positive-OR
    3. Positive-OR, Negative-AND
    4. Positive-OR, Positive-AND

30. PALs tend to execute ________ logic.

    1. SPD
    2. SOP
    3. SAC
    4. SAP

Select a course code for Objective Questions:

ACC311 ACC501 BIF101 BIF401 BIF501 BIO101 BIO201 BIO202 BIO203 BIO204 BIO301 BIO302 BIO303 BIO401 BIO503 BNK603 BT101 BT201 BT301 BT302 BT401 BT402 BT403 BT404 BT405 BT406 BT501 BT504 BT505 BT604 CHE201 CHE301 CS001 CS101 CS201 CS202 CS204 CS301 CS302 CS304 CS311 CS401 CS402 CS403 CS408 CS501 CS502 CS504 CS506 CS508 CS601 CS602 CS604 CS605 CS607 CS609 CS610 CS614 CS707 CS710 ECO401 ECO402 ECO403 ECO404 EDU302 EDU401 EDU402 EDU501 EDU601 ENG101 ENG201 ENG301 ENG501 FIN611 FIN624 FIN625 ISL201 IT430 MCM101 MCM301 MGMT623 MGT101 MGT211 MGT301 MGT401 MGT402 MGT501 MGT502 MGT503 MGT510 MGT601 MGT603 MKT501 MKT610 MKT630 MTH101 MTH202 MTH302 MTH501 MTH601 MTH634 PAK301 PHY101 PHY301 PSY101 PSY403 PSY502 PSY512 SOC101 SOC301 SOC401 STA301 STA630 STA641 ZOO102 ZOO401 ZOO501 ZOO502 ZOO503 ZOO504 ZOO505 ZOO506 ZOO510 ZOO630

Select a course code for Subjective Questions:

ACC311 CS001 CS101 CS201 CS301 CS607 CS701 CS702 CS703 CS704 CS707 CS708 CS710 CS711 CS718 CS721 CS724 ECO401 ECO403 ENG101 ENG301 MGT703 MTH501 STA301