Multiple Choice Questions (MCQs)
The Synchronous SRAM also has a Burst feature which allows the Synchronous SRAM to read or write up to ________ location(s) using a single address.
Consider A=1, B=0, C=1. A, B and C represent the input of three bit NAND gate, the output of the NAND gate will be ________.
Memory is arranged in ________.
In NAND based S-R latch, output of each ________ gate is connected to the input of the other ________ gate.
In memory write cycle, the time for which the WE signal remains active is known as the ________.
In distributed mode, for a 1024 x 1024 DRAM memory and a refresh cycle of 8 msec, each of the 1024 rows has to be refreshed in ________ when Distributed refresh is used.
The output of a NAND gate is ________ when all the inputs are one.
Subtractors also have output to check if 1 has been ________.
________ is used when the output is connected back to the input of the PAL or if the output pin is used as an input only.
Consider the sum of weight method for converting decimal into binary value, ________ is the highest weight for 411.
The ROM used by a computer is relatively ________ as it stores few byres of code used to Boot the Computer system on power up.
As data values are written or read from the RAM Stack Pointer Register increments or decrements its contents always pointing to the stack ________.
If the voltage drop across the active load is 0 volts due to absence of current the comparator output is a ________.
A NOR based S-R latch is implemented using ________ gates instead of ________ gates.
In DRAM read cycle R /W- signal is activated to read data which is made available on the ________ data line.
The 74HC163 is a 4-bit Synchronous counter, it has ________ data output pins.
You have to choose suitable option when your timer will reset by considering this given code: TRSTATE.CLK = clk; TMRST: = (TRSTATE = = NSY2) # (TRSTATE = = EWY2);
Which of the following is a volatile memory?
The terminal count of a 4-bit binary counter in the UP mode is ________.
The outputs of SR latches in elevator state machine are feed back to the ________ gate array for connection to the D-flipflops.
An Asynchronous Down-counter is implemented (Using J-K flip-flop) by connecting ________.
In case of cascading Integrated Circuit counters, the enable inputs and RCO of the Integrated Circuit counters allow cascading of multiple counters together.
For a down counter that counts from (111 to 000), if current state is "101" the next state will be ________.
________ Counters as the name indicates are not triggered simultaneously.
A multiplexer with a register circuit converts
The ________ gate and ________ gate implementation connected at the B input of the 4-bit Adder is used to allow Complemented or Un-Complemented B input to be connected to the Adder input.
GAL can be reprogrammed as instead of fuses E2CMOS logic is used which can be programmed to connect a ________ with a ________.
PALs tend to execute ________ logic.
8-bit parallel data can be converted into serial data by using ________ multiplexer.
If the number of samples that are collected is reduced by half, the reconstructed signal will be ________ from/to the original.
The ________ input overrides the ________ input.
For a Standard SOP expression, a ________ is placed in the cell corresponding to the product term (Minterm) present in the expression.
Cin is part of ________ Adder.
Which one flip-flop has an invalid output state?
The FAST Model Page Access allows ________ memory read and access times when reading successive data values stored in consecutive locations on the same row.
The CONSTATE.CLK = Clock is used to indicate that the ________ state variables change on a clock transition.
The ABEL Input file can use a ________ instead of the equation to specify the Boolean expressions.
Divide-by-32 counter can be achieved by using
The n flip-flops store ________ states.
Canonical form is a unique way of representing ________.
Flash memory Operation are classified into ________ different operation.
Demorgan's two theorems prove the equivalency of the NAND and ________ gates and the NOR and ________ gates respectively.
The Transition table is very similar to the ________ table.
The maximum value, represented by a single hexadecimal digit is ________.
The normal data inputs to a flip-flop (D, S and R, J and K, T) are referred to as ________ inputs.
In the keyboard encoder, how many times per second does the ring counter scan the key board?
Two types of memories namely the first in-first out (FIFO) memory and last in first out (LIFO) are implemented using ________.
The AND Gate performs a logical ________ function.
Which of the following Output Equations determines the output of the State Machine?
Adding two octal numbers "36" and "71" result in ________.
PLDs have In-System Programming (ISP) capability that allows the ________ to be programmed after they have been installed on a circuit board.
A SOP expression can be implemented by an ________ combination of gates.
Implementation of the FIFO buffer in ________ is usually takes the form of a circular buffer.
Which signal must remain valid in memory write cycle after data is applied at the data input lines and must remain valid for a minimum time duration tWD?
If two numbers in BCD representation generate an invalid BCD number then the binary ________ is added to the result.
A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN mode is:
When the transmission line is idle in an asynchronous transmission
Implementation of Latch is required almost ________ transistor.
Why demultiplexer is called a data distributor?
A decade counter can be implemented by truncating the counting sequence of a MOD-20 counter.
The NOR logic gate is the same as the operation of the ________ gate with an inverter connected to the output.
The Static Ram (SRAM) is non-volatile and is not a ________ density memory as a latch is required to store a single bit of information.
The domain of the expression AB'CD + AB' + C'D + B is
Implementing the Adjacent 1s detector circuit directly from the function table based on the SOP form requires ________ gates for the 8 product terms (minterms) with an 8-input OR gate.
The Test Vector definition defines the test vectors for all the three counter inputs and ________ counter output/outputs.
A 3-variable karnaugh map has
Select the mode of programming in which GAL16V8 can be programmed:
The 64-cell array organized as 8 x 8 cell array is considered
UVERPROM is stands for
The next state table for REQ1, FLOOR1 and OPEN inputs indicates that the ________ can be pressed at any time either on the first floor or the second floor in elevator.
Two signals ________ and ________ provide the timing inputs to the State Machine.
The Adjacent 1s Detector accepts 4-bit inputs. If ________ adjacents 1s are detected in the input, the output is set to high.
The S-R latch has two inputs, therefore ________ different combinations of inputs can be applied to control the operation of the S-R latch.
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